The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Shallow trench insulators (STI) provide electrical isolation between individual transistor devices in integrated circuits (ICs). STIs usually include trenches that are filled with high quality silicon dioxide (SiO2) film. In some examples, an aspect ratio (AR) of the trench can be as high as 8:1 and an opening of the trench narrows down to 20 nm. Void free STI gap fill during processing is important because the substrate may be subjected to a wet chemical process during subsequent integration steps.
Conventionally, STIs are filled using a high density plasma chemical vapor deposition (HDPCVD) process. For trenches with AR greater than about 4:1, the HDPCVD oxide is unable to fill the STIs without voids. Voids occur even when a cyclic deposition-etch-deposition process is used.
Alternative filling techniques such as sub-atmospheric CVD (SACVD) have been used. However, SACVD is sensitive to fill profile because SACVD is less than 100% conformal. Emerging flowable oxide processes provide liquid-like filling behavior but the film quality is largely limited by the high carbon content present in the film.